Datasheet

UCC27323, UCC27324, UCC27325

UCC37323, UCC37324, UCC37325

SLUS492H –JUNE 2001–REVISED MAY 2013

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Operational Waveforms and Circuit Layout

Figure 5 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load.

The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the

linear rise and fall edges of the switching waveforms which is due to the constant output current characteristic of

the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.

Sink and source currents of the driver are dependent upon the VDD value and the output capacitive load. The

larger the VDD value, the higher the current capability; also, the larger the capacitive load, the higher the current

sink and source capability.

Trace resistance and inductance, including wires and cables for testing, slows down the rise and fall times of the

outputs; thus reducing the current capabilities of the driver.

To achieve higher current results, reduce resistance and inductance on the board as much as possible and

increase the capacitive load value in order to swamp out the effect of inductance values.

Figure 5.

In a power driver operating at high frequency, a significant challenge is to get clean waveforms without much

overshoot or undershoot and ringing. The low output impedance of these drivers produces waveforms with high

di/dt, which tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.

Connecting the driver IC as close as possible to the leads is advantageous. The driver IC layout has ground on

the opposite side of the output, so the ground is connected to the bypass capacitors and the load with copper

trace as wide as possible. These connections are also made with a small enclosed loop area to minimize the

inductance.

Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325