Datasheet

UCC27321-Q1, UCC27322-Q1
www.ti.com SLUSA13C –FEBRUARY 2010–REVISED MARCH 2012
When a driver is tested with a discrete capacitive load, it is a fairly simple matter to calculate the power that is
required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
E = ½CV
2
where C is the load capacitor and V is the bias voltage feeding the driver.
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by:
P = 2 × ½CV
2
f
where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate-drive waveform should help clarify this.
With V
DD
= 12 V, C
LOAD
= 10 nF, and f = 300 kHz, the power loss can be calculated as:
P = 10 nF × (12)
2
× (300 kHz) = 0.432 W
With a 12-V supply, this equates to a current of:
I = P / V = 0.432 W / 12 V = 0.036 A
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the on and off states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Q
g
, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Q
g
= CeffV to provide the following equation for
power:
P = C × V
2
× f = Q
g
× V × f
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
ENABLE
UCC37321/2 provides an enable input for improved control of the driver operation. This input also incorporates
logic-compatible thresholds with hysteresis. The input is internally pulled up to VDD with a 100-kΩ resistor for
active-high operation. When ENBL is high, the device is enabled, and when ENBL is low, the device is disabled.
The default state of the ENBL pin is to enable the device, and therefore can be left open for standard operation.
The output state when the device is disabled is low, regardless of the input state. See the truth table (Table 2) for
operation using enable logic.
The ENBL input is compatible with both logic signals and slow-changing analog signals. It can be directly driven,
or a power-up delay can be programmed with a capacitor between ENBL and AGND.
Table 2. Input/Ouput Table
ENBL IN OUT
0 0 0
0 1 0
Inverting UCC37321
1 0 1
1 1 0
0 0 0
0 1 0
Non-inverting UCC37322
1 0 0
1 1 1
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