Datasheet
SLUS486B − AUGUST 2001 − REVISED JULY 2003
5
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TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 6 −
Analog ground for all internal logic circuitry. AGND and PGND should be tied to the PCB ground plane
with vias.
G1 13 O High-side gate driver output that swings between SW and VHI.
G2 9 O Low-side gate driver output that swings between PGND and PVLO.
G2S 10 I
Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the
appropriate deadtime.
IN 7 I
Digital input command pin. A logic high forces on the main switch and forces off the synchronous
rectifier.
PGND 8 − Ground return for the G2 driver. Connect PGND to PCB ground plane with several vias.
PVLO 5 I PVLO supplies the G2 driver. Connect PVLO to VLO and bypass on the PCB.
SW 12 − G1 driver return connection.
SWS 11 I
Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain
close to the MOSFET package.
VDD 3 I
Input to the internal VLO regulator. Nominal VDD range is from 8.5 V to 20 V. Bypass with at least
0.1 µF of capacitance.
VHI 14 I
Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on-time.
Bypass VHI to SW with an external capacitor.
VLO 4 O
Output of the VLO regulator and supply input for the logic and control circuitry. Connect VLO to PVLO and
bypass on the PCB.
SIMPLIFIED BLOCK DIAGRAM
UDG−01030
N/C
N/C
VDD
VLO
PVLO
1
2
3
4
5
VLO
REGULATOR
+
3.82 V/ 3.7 V
UVLO
PREDICTIVE
DELAY
CONTROLLER
14
13
12
11
10
9
VHI
G1
SWS
SW
G2S
G2
AGND
IN
6
7
PVLO
PVLO
8 PGND
VLO
UCC27221
UCC27222