Datasheet
SLUS486B − AUGUST 2001 − REVISED JULY 2003
18
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LAYOUT CONSIDERATIONS
packaging
The UCC27221/2 are only available in TI’s thermally enhanced 14-pin PowerPad package. This package
offers exceptional thermal impedance with a junction-to-case rating of 2C/W. Shown as the crosshatched
region in Figure 16, PowerPad includes an exposed leadframe die pad located on the bottom side of the
package. Exposed pad dimensions for the PowerPad TSSOP 14-pin package are 69 mils x 56 mils (1.8 mm
x 1.4 mm). However, the exposed pad tolerances can be + 41 / − 2 mils (+ 1.05 /− .05 mm) due to position and
mold flow variation. Effectively removing the heat from the PowerPAD package requires a thermal land area,
shown as the shaded gray region in Figure 16, designed into the PCB directly beneath the package. A minimum
thermal land area of 5 mm by 3.4 mm is recommended as illustrated in Figure 16. Any tolerance variances of
the exposed PowerPad falls well within the thermal land area when the recommended minimum land area
is included on the printed circuit board. In addition, a 2-by-3 array of 13-mil thermal vias is required within the
exposed PowerPad area, as shown in Figure 16. If additional heat sinking capability is required, larger 25-mil
vias can be added to the thermal land area.
3.4mm
(0.1339”)
0.65mm
(0.0256”)
0.3mm
(0.0118”)
1.05mm
(0.0413”)
Exposed
PowerPad
1.4mm (0.056”)
Exposed
PowerPad
1.8mm (0.069”)
5.0mm
(0.1968”)
Required Vias on PowerPad Area
2 x 3 Array
0.33mm
(13 mil) dia Vias
Optional Vias on Thermal Land Area
0.635mm
(25 mil) dia Vias
Figure 16. TSSOP−14PWP Package Outline and Minimum PowerPADE PCB Thermal Land