Datasheet

UCC27210
UCC27211
www.ti.com SLUSAT7E –NOVEMBER 2011–REVISED AUGUST 2013
Input Stages
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27210 is 100
kΩ nominal and input capacitance is approximately 2 pF. The 100 kΩ is a pull-down resistance to V
SS
(ground).
The UCC27210 Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same
time to allows interfacing to a multitude of analog or digital PWM controllers. In some CMOS designs, the input
thresholds are determined as a percentage of VDD. By doing so, the high-level input threshold can become
unreasonably high and unusable. The UCC27210 recognizes the fact that VDD levels are trending downward
and it therefore provides a rising threshold with 5.0 V (typ) and falling threshold with 3.2 V (typ). The input
hysteresis of the UCC27210 is 1.8 V (typ).
The input stages of the UCC27211 have impedance of 70 kΩ nominal and input capacitance is approximately 2
pF. Pull-down resistance to V
SS
(ground) is 70 kΩ. The logic level compatible input provides a rising threshold of
2.3 V and a falling threshold of 1.6 V.
Under Voltage Lockout (UVLO)
The bias supplies for the high-side and low-side drivers have UVLO protection. V
DD
as well as V
HB
to V
HS
differential voltages are monitored. The V
DD
UVLO disables both drivers when V
DD
is below the specified
threshold. The rising V
DD
threshold is 7.0 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the V
HB
to V
HS
differential voltage is below the specified threshold. The V
HB
UVLO rising threshold is
6.7 V with 1.1-V hysteresis.
Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC27210/11 family of drivers. The
diode anode is connected to V
DD
and cathode connected to V
HB
. With the V
HB
capacitor connected to HB and the
HS pins, the V
HB
capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot
diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from V
DD
to V
SS
and the high side is referenced from V
HB
to V
HS
.
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