Datasheet

UCC27200 , UCC27201
www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008
Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason
the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is
specified as 0.18 V at 100-mA dc current implying 1.8- Ω R
DS(on)
. With 12-V drive voltage, no parasitic inductance
and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side
drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current
waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver
MOSFET ’ S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately
3.3 A as shown in Figure 18 . The overall parasitic inductance of the drive circuit is estimated at 4 nH. The
internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads. The
SON-8 package reduces the internal parasitic inductances by more than 50%.
Actual measured waveforms are shown in Figure 26 and Figure 27 . As shown, the typical rise time of 8 ns and
fall time of 7 ns is conservatively rated.
Figure 26. V
LO
and V
HO
Rise Time, 1-nF Load, 5 ns/Div Figure 27. V
LO
and V
HO
Fall Time, 1-nF Load, 5-ns/Div
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