Datasheet

Design Tips
Switching the MOSFETs
7
8
Vss
1
VDD
LO
Cvdd
L bondwire
Rsink
Rsource
L pin
L trace
L bondwire
L bondwire
Driver
Output
Stage
L pin
L pin
L trace
Isink
L trace
Cgs
Rg
L trace
ISOURCE
UCC27200 , UCC27201
www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008
Achieving optimum drive performance at high frequency efficiently requires special attention to layout and
minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB
layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance
elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its
CGS capacitance.
Figure 23. MOSFET Drive Paths and Circuit Parasitics
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