Datasheet

UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011– REVISED DECEMBER 2011 www.ti.com
PIN FUNCTIONS
PIN
I/O DESCRIPTION
PIN NAME DRM/D/DDA DRC DPR
Positive supply to the lower gate driver. De-couple this pin to
VDD 1 1 1 I VSS (GND). Typical decoupling capacitor range is 0.22 μF to
1.0 μF.
High-side bootstrap supply. The bootstrap diode is on-chip but
the external bootstrap capacitor is required. Connect positive
HB 2 2 2 I side of the bootstrap capacitor to this pin. Typical range of HB
bypass capacitor is 0.022 μF to 0.1 μF, the value is dependant
on the gate charge of the high-side MOSFET however.
High-side output. Connect to the gate of the high-side power
HO 3 3 3 O
MOSFET.
High-side source connection. Connect to source of high-side
HS 4 4 4 I power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI 5 6 7 I High-side input.
LI 6 7 8 I Low-side input.
Negative supply terminal for the device which is generally
VSS 7 8 9 O
grounded.
Low-side output. Connect to the gate of the low-side power
LO 8 9 10 O
MOSFET.
N/C - 5 5/6 - No connection. Pins labeled N/C have no connection.
Connect to a large thermal mass trace or GND plane to
PowerPAD™ Pad
(1)
Pad Pad -
dramatically improve thermal performance.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DDA and DRM packages only. Electrically referenced to VSS
(GND).
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