Datasheet

Boot Diode Performance
Layout Recommendations
UCC27200 , UCC27201
www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008
The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high side bias
internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc
characteristics to consider are V
F
and dynamic resistance. A low V
F
and high dynamic resistance results in a
high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V
V
F
and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic
characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified
with no conditions can be misleading. Diode recovery times at no forward current (I
F
) can be noticeably less than
with forward current applied. The UCC2720x boot diode recovery is specified at 20ns at I
F
= 20 mA, I
REV
= 0.5 A.
At 0 mA I
F
the reverse recovery time is 15 ns.
Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every
switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to
charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the
voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often
less than a comparable Schottky diode.
To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.
• Locate the driver as close as possible to the MOSFETs.
• Locate the V
DD
and V
HB
(bootstrap) capacitors as close as possible to the driver.
• Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by
connecting it to the VSS pin (GND). Note: The GND trace from the driver goes directly to the source of the
MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.
• Use similar rules for the HS node as for GND for the high side driver.
• Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is
preferable where possible.
• Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.
For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic
inductance.
• Avoid L
I
and H
I
(driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
• Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can
even lead to decreased reliability of the whole system.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): UCC27200 UCC27201