Datasheet

Delay Matching and Narrow Pulse Widths
UCC27200 , UCC27201
SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com
The total delays encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The sync-buck topology switching
requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and
2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the
transformer if there is imbalance in the high and low side pulse widths in a steady state condition.
Narrow pulse width performance is an important consideration when transient and short circuit conditions are
encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very
narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions.
The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and
narrow pulse width performance. The delay matching waveforms are shown in Figure 31 and Figure 32 . The
UCC2720x driver narrow pulse performance is shown in Figure 33 and Figure 34 .
Figure 31. V
LO
and V
HO
Rising Edge Delay Matching Figure 32. V
LO
and V
HO
Falling Edge Delay Matching
Figure 33. 20-ns Input Pulse Delay Matching Figure 34. 10-ns Input Pulse Delay Matching
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