Datasheet

2
UCC1583
UCC2583
UCC3583
ABSOLUTE MAXIMUM RATINGS
V
DD
.......................................... 15V
I
VDD
.........................................15mA
RAMP .............................–0.3V to V
DD
+1V
I
RAMP
.........................................5mA
I
REF
....................................................
–30mA
P
COM ..................................–0.2V to 0.2V
I
GATE
(twp < 1µS and Duty Cycle < 10%) ...... –0.8A to 1.8A
I
COMP
..................................–5mA to 5mA
I
CAO
...................................–5mA to 5mA
V
SYNC
............................–0.6V to V
REF
+0.3V
I
SYNC
.................................–05mA to 5mA
INV, SS, ILIM, ISENSE..............–0.3V to VREF + 0.3V
Storage Temperature ...................–65°C to +150°C
Junction Temperature...................–55°C to +150°C
Lead Temperature (Soldering, 10 sec.) .............+300°C
All voltages are with respect to the COM terminal unless other
-
wise stated. Currents are positive into, negative out of the
specified terminal. Consult Packaging Section of Databook for
thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-14, SOIC-14 (Top View)
J, N, or D Packages
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for T
A
= –55°Cto125°C for
UCC1583, –40°C to 85°C for UCC2583, and 0°C to 70°C for UCC3583; VDD = 12V, R
T
= 60k, C
T
= 100pF, T
A
=T
J
.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Ramp Generation and Synchronization
Maximum Input Operating Frequency For input with 5% to 90% duty cycle (Note 1) 500 kHz
Ramp Frequency, Free Running T
A
= 25°C 95 100 105 kHz
T
A
= -55°C to 125°C 90 100 110 kHz
Ramp Discharge Current V
RAMP
= 0.5V 2.0 3.6 mA
Low Threshold Voltage No min, no max, 0=TYP 0 V
High Threshold Voltage 3.75 4 4.25 V
Synchronizing Threshold Voltage (On) (Note 1) 1 V
Synchronizing Comparator Hysteresis 1 V
PLCC-20 (Top View)
Q Package
PACKAGE qja qjc
N-14 90 45
J-14 90-120 28
D-14 50-120 35
PLCC-20 43-75 34
Note 1. qja (junction to ambient) is for devices mounted to 5 in2
FR4 PC board with one ounce copper where noted. When re-
sistance range is given, lower values are for 5 in2 aluminum
PC board. Test PWB was .062 in thick and typically used 0.635
mm trace widths for power pkgs and 1.3 mm trace widths for
non-power pkgs with a 100x100 mil probe land area at the end
of each trace
Note 2. qjc data values stated were derived from
MIL-STD-1835B. MIL-STD-1835B states that “The baseline
values shown are worst case (mean + 2s) for a 60x60 mil
microcircuit device silicon die and applicable for devices with
die sizes up to 14400 square mils. For device die sizes greater
than14400 square mils use the following values; dual-in-line,
11°C/W; flat pack, 10°C/W; pin grid array, 10°C/W”.
THERMAL IMPEDANCE