Datasheet

UCC25705, UCC25706, UCC35705, UCC35706
HIGH-SPEED VOLTAGE MODE PULSE WIDTH MODULATOR
SLUS473B -- NOVEMBER 1999 -- REVISED OCTOBER 2010
5
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pin descriptions (continued)
7
2
5
8
OUT
VDD
6GND
SQ
Q
RD
RD
RD
1ILIM
200 mV
CURRENT LIMIT
1pF20 k
Ω
30 k
Ω
+
0.7 V
PWM
S
Q
QRD
CLK
PWM
LATCH
100 mV
2*I(MODE=1)
0(MODE=0)
LOW LINE
1.0 V
30 * I (MODE=1)
80
Ω
(MODE = 0)
I
RC
VFF
FB
3
DISCH
4
50 mV
VDD
MODE
UCC35705 (8.8 V/8 V)
UCC35706 (12 V/8 V)
UVLO
+
--
+
--
+
--
+
--
+
--
+
--
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION
oscillator and PWM
The oscillator can be programmed to provide a duty cycle clamp or be configured to run at the maximum possible
duty cycle.
The PWM latch is set during the oscillator discharge and is reset by the PWM comparator when the C
T
waveform
is greater than the feedback voltage. The voltage at the FB pin is attenuated before it is applied to the PWM
comparator. The oscillator ramp is shifted by approximately 0.65-V at room temperature at the PWM comparator. The
offset has a temperature coefficient of approximately --2 mV/°C.
The ILIM c omparator adds a pulse by pulse current limit by resetting the PWM latch when V
ILIM
> 200 mV. The PWM
latch is also reset by a low line condition (V
FF
<1.0 V).
All reset conditions are dominant; asserting any output will force a zero duty cycle output.
oscillator with duty cycle clamp (MODE = 1)
The timing capacitor CT is charged from ground to VFF through RT. The discharge path is through an on-chip current
sink that has a value of 30 × I
DISCH
, where I
DISCH
is the current through the external resistor RDISCH. Since the
charge and discharge currents are both proportional to VIN, their ratio, and the maximum duty cycle remains constant
as VIN varies.