Datasheet

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4.1 Circuit Description
Diode bridge D1, input capacitor C5, transformer (a.k.a. flyback inductor) T1, HV MOSFET Q2, UCC28610
controller U3, synchronous rectification MOSFET Q1, output capacitors C8, C9, and C10 form the power
stage of the converter. Note that the UCC28610 U3 is part of the power stage. This is because the DRV
and GND pins carry the full-peak primary-side current of the converter.
UCC24610 controller U1 drives the synchronous rectification MOSFET Q1, R11 sets the minimum time
that Q1 will remain off, ignoring any resonant ringing that may inadvertently trigger the turn-on detection
circuit. Resistor R12 performs a similar function in regards to the on-time of Q1 by programming the
minimum time that Q1 will remain on despite any ringing due to noise that may inadvertently trigger a
turn-off response. Resistor R9 dampens any resonant tank ringing on the gate of Q1. To reduce the
current drawn out of VD, resistor R5 is added between VD and the drain of Q1. Because VD and VS are
inputs to a differential comparator, a resistor, R8, is also needed between VS and the source of Q1.
Bench testing concluded that using a slightly larger value for R8 on VS extended the on-time of Q1, and
reduced the body diode conduction time.
Capacitors C6, C7, and C12 filter the high-frequency noise directly across the electrolytic input and output
capacitors.
The input EMI filter is made up of X2 capacitors, C3 and C4, and common mode inductor L1. Excessive
surge current protection is provided by a slow blow fuse, F1.
Resistor R1, capacitor C1, and diode D2 make up the primary side voltage clamp for the HV MOSFET.
The clamp prevents the drain voltage on Q2 from exceeding its maximum rating. The integrated snubber,
composed of R2 and C1, reduces the ringing on the primary-side windings that might inadvertently trigger
the light-load shutdown point of the UCC24610 gate drive.
Resistors R4, R6, and R7 supply start-up bias current to the VGG shunt regulator of U3. Schottky diode
D5 is required to provide initial start up to VDD from VGG at start up.
Operating bias to the UCC28610 controller is provided by the auxiliary winding on T1, diode D3, and bulk
capacitor C16. The zener diode, D7, maintains the bias voltage on U3 VDD below the absolute maximum
rating at full load.
Primary switch gate drive circuitry is composed of gate drive resistor R13, used for damping oscillations
during turn on. Resistor R14 and diode D4 are required to provide a current path at turn off because the
gate is shorted to the source of the HV MOSFET during each switching cycle. Ferrite bead FB1 reduces
the high ringing on VGG at turn off.
Capacitors C17, C18, and C13 are decoupling capacitors which should always be good quality low
ESR/ESL type capacitors placed as close to the controller device pins as possible and returned directly to
the device ground reference.
C2 filters the common mode noise between the primary and secondary sides.
Inductor L2, with capacitor C11, reduces the output voltage ripple.
Resistors R19 and R21 program the over voltage threshold. Capacitor C15 can be used to add a small
delay to U3 ZCD, to align the turn-on time of the primary switch with the resonant valley of the primary
winding.
Resistor R23 programs the maximum on time of the primary side HV MOSFET.
Resistor R22 sets the maximum value for the peak-primary current.
Resistor R18 and capacitor C14 provide a filter for the U3 FB signal while resistor R20 ensures that the
optocoupler emitter current can go to 0 A. Output voltage regulation is provided by diode D6, resistors R15
and R17, and the optocoupler U2. Using an opto with a low current transfer ratio provides better noise
immunity. Resistor R10 is used as an injection point for small signal frequency response testing.
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5-V, 25-W Flyback Converter With Secondary-Side Synchronous Rectification SLUU434–August 2010
Copyright © 2010, Texas Instruments Incorporated