Datasheet

(t)
(A), (V)
Primary-Side PWM Output
TOFF Blanking
I
SEC
V
DS
GATE Output
TON Blanking
SYNC Signal
V
DS
> V
THARM
Detection
V
DS
> V
THOFF
Detection
V
DS
< V
THON
Detection
ARMED
UDG-10088
UCC24610
www.ti.com SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010
6. The C
SYNC
Capacitor Resets
The C
SYNC
capacitor resets during the off-time of the primary-side MOSFET, while the SR-FET is conducting.
The reset current i
SYNC_RESET
is similar to i
SYNC
. However, this reset current flows through the internal diode
between SYNC and VCC pins of the device.
Figure 24. External and Internal Signal Timing Relationships with Respect to Realistic CCM Waveforms
Single-Fault Self-Protection Features
If R
TON
is less than 8.7 kΩ, the device may detect excess current and interpret this as a short-cir cuit and disable
the GATE output.
If R
TON
is greater than 301 kΩ, the device may detect insufficient current and interpret this as an open-circuit and
disable the GATE output, to avoid indefinite on-time.
Noise pick-up on excessive trace length may destabilize the internal 2-V source causing either insufficient or
excess current to R
TON
and triggering premature GATE shut off. This could cause GATE output to be less than
TON and lead to Light-Load Mode even at heavy loads. Minimize R
TON
trace lengths.
If R
EN/TOFF
is less than 93 kΩ, the device may detect insufficient voltage for Enable threshold and disable the
GATE output.
If R
EN/TOFF
is greater than 284 kΩ, the device will internally clamp the programming voltage to deliver a minimum
T
OFF
of ~0.65 µs, regardless of R
EN/TOFF
value.
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