Datasheet
MIN
SYNC
SYNC SYNC
1.5 t
C
R r
´
=
+
SYNC
SYNC
1.5 40ns
C
R 2k
´
=
+ W
[ ]
SYNC
2
SYNC pri max
r SYNC SYNC SYNC SW
SYNC SYNC pri min
V
(VCC 0.7 V)
P ln 1 (R r ) C f
r V
- -
- -
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D
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+
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ç ÷
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ç ÷
D
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ë û
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ë û
SYNC
2
R SYNC BULK RESET SPIKE SW
1
P 2 C (V V V ) f
2
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PIN
PIN _ DLY
SYNC
2 V C
t
i
´
=
f SYNC
dV _ DLY
SYNC SYNC
t R
t
R r
D ´
=
+
OFF _ DLY SDLY PIN _ DLY dV _ DLY
t t t t= + +
UCC24610
SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
2. After the ΔV
DS_PRI
Transition
After the ΔV
DS_PRI
transition, the SYNC signal will begin to reset back to VCC by charging exponentially. This
allows the value of the SYNC coupling capacitor C
SYNC
to be determined by:
(13)
The value of C
SYNC
is chosen to ensure that the SYNC signal stays below the SYNC threshold for at least 20 ns.
Choose the minimum dwell time t
MIN
to be 40 ns to allow for parametric variations, so in this case:
(14)
3. The value of C
CM
The value of C
CM
should be much higher than that of C
SYNC
. If necessary, increase the value of C
CM
to ensure
that C
CM
>> C
SYNC
; do not decrease C
SYNC
.
4. Conservative Power-Loss Estimates
Conservative power-loss estimates for the internal and external SYNC resistances are:
(15)
and
(16)
where f
SW
is the converter switching frequency. These calculations can be used to predict the maximum thermal
impact of the SYNC current on the device junction temperature and to determine the external SYNC resistor
power rating. Actual SYNC-related losses generally are lower than these calculations predict and observations of
actual circuit operation should be used to determine true losses if more accuracy is required.
5. The Device Internal SYNC-to-GATE Delay Time
The device internal SYNC-to-GATE delay time t
SDLY
is a measure of how quickly the GATE output will turn off
after the SYNC signal has crossed the V
THSYNC
threshold. However, stray pin capacitance C
PIN
introduces an
additional delay to the SYNC function by slowing the SYNC voltage falling 2 V below VCC. If C
PIN
is small, this
delay is relatively short and the SYNC current can be approximated as a constant current, allowing this
calculation to simplify to a simple linear equation given by:
(17)
Also, additional delay comes from the finite dV/dt of the signal source, in this case V
DS_PRI
, due to the finite
transition time from V
BULK
level to 0 V. This delay can be approximated by:
(18)
These delay times should be added to the internal SYNC-to-GATE delay (specified in the datasheet) to
determine the total delay time expected between the falling of the primary-side MOSFET drain voltage and the
turn off of the SR-FET gate drive.
(19)
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