Datasheet

V
RESET
V
BULK
V
SPIKE
80%
20%
Δt
f
UDG-10089
SYNC pri
SYNC SYNC
SYNC
V
R r
i (min)
-
D
£ -
BULK
SYNC
V (min)
R 2k
2mA
£ - W
UCC24610
www.ti.com SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010
C
SYNC
is the synchronization signal coupling capacitor, rated to cross the primary-to-secondary isolation
boundary. It is used to couple a negative-going voltage into the UCC24610 SYNC input (pin 1) to turn off the
GATE output to the SR-MOSFET when the primary-side MOSFET is turned on.
R
SYNC
is an optional external current-limiting resistor used to reduce the peak current into the SYNC input. It also
serves to reduce overall power loss, and reduce the common-mode noise current.
C
CM
is the main common-mode capacitance between the primary and the secondary sides of the system. This is
usually a discrete component, whose value ranges from 100 pF ~ 2200 pF. Aside from any EMI-control
purposes, it also serves as the return path for the SYNC signal charging and discharging current pulses across
the isolation boundary.
Within the UCC24610 controller device is a 2-kΩ pull-up resistor (r
SYNC
) to VCC. To trigger the SYNC function, a
negative-going signal must pull the SYNC input below the V
THSYNC
threshold (nominally 2 V below VCC) for a
minimum duration of 20 ns. This requires a minimum 1-mA current to achieve, but prudent design will target a
higher current to allow for parameter variations.
Internal clamp diodes to VCC and GND also form parts of the charging and discharging current paths of the
SYNC signal. Finally, C
PIN
comprises stray internal and external pin and pad capacitances on the SYNC input,
and is modeled as ~10 pF to GND. Although C
PIN
is physically unavoidable, it is wise to minimize any external
stray capacitance to keep its effect of additional delay on the SYNC function to a minimum.
1. Determine the Minimum Change
Determine the minimum change in voltage ΔV
SYNC-pri
expected from the SYNC signal source. In this example, the
primary-side MOSFET drain-to-source voltage V
DS_PRI
is the signal source, and its minimum change is V
BULK(min)
at low input line.
Figure 23. Primary MOSFET Drain Voltage
ΔV
DS_PRI
= V
BULK
at low-line. Δt
f
= fall time for ΔV
DS_PRI
between the 80% and 20% points.
V
SYNC-pri
= ΔV
DS_PRI
To allow for parameter and environmental variations, set the minimum peak SYNC current to be 2 mA. With 2
mA peak flowing through the internal 2-kΩ resistor, the SYNC voltage falls to 4 V below VCC. The maximum
value for current limiting resistor R
SYNC
is determined by:
(11)
so in this case,
(12)
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