Datasheet

23758
1
4
VD GATE VS TON EN/TOFF
VCC
SYNC
6
GND
C
PIN
r
SYNC
To Control Logic
VCC
UCC24610
R
SYNC
C
SYNC
C
CM
i
SYNC_RESET
i
SYNC
5 V OUT
UDG-10090
UCC24610
SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010 www.ti.com
SYNC Input Considerations
In applications where the synchronous rectifier is used in Continuous Conduction Mode (CCM) such as
CCM-Flyback and LLC converters, it is imperative that the SR-MOSFET be turned off as soon as the
primary-side switch turns on, to prevent reverse conduction of the SR-MOSFET. In these applications, a Y-type
isolating capacitor C
SYNC
can be used to convey a primary-side signal to the SR controller by coupling a
negative-going trigger voltage into the SYNC pin. Alternatively, an isolating pulse transformer may be used in
situations where a coupling capacitor is not practicable. When the SYNC voltage falls 2 V below VCC (the SYNC
detection threshold V
THSYNC
), the GATE output is immediately turned off, regardless of the state of the TON
timer. An internal 2-kΩ pull-up resistance (r
SYNC
) provides current to recharge the SYNC coupling capacitor. In
the event that the SYNC input voltage is continuously held below V
THSYNC
, the GATE output is driven low for the
same duration.
The SYNC input has a maximum pulse current rating of ±100 mA, and a high-reliability design should reduce the
peak current further. This also reduces noise and signal losses in the system. A series resistor helps limit the
pulse current by reducing the effective dV/dt across C
SYNC
. Figure 22 illustrates a simple implementation of the
SYNC signal derived from the falling drain-source voltage of the primary-side MOSFET. In this example, a
synchronous-rectifier MOSFET is used in place of the free-wheeling diode in a single-transistor forward-mode
application. Note that primary-to-secondary common-mode capacitance CCM forms the return path for the SYNC
current.
Nominally, only -1 mA is required to develop -2 V across the internal 2-kΩ resistance and trigger the SYNC
function. This current is generated by a rapidly changing voltage across the SYNC coupling capacitor C
SYNC
. But
variations of this resistor, of C
SYNC
, and of the dV/dt across C
SYNC
require that worst-case tolerances be taken
into account when determining the minimum value of C
SYNC
. In addition, V
SYNC
must exceed the V
THSYNC
threshold for a minimum duration of 20 ns to ensure that the internal controller logic has reliably triggered.
Although the TON minimum on-time gate-drive function is overridden by the SYNC signal, the timer continues to
function otherwise. Light-Load Mode is entered if the proper conditions are met, as usual. The TOFF timer is
triggered when the SR-MOSFET V
DS
exceeds 1.5 V, as usual.
Figure 22. Driving the SYNC Input from the Primary-Side MOSFET Drain
22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC24610