Datasheet

GATE g

iss

R 2 r

³ -

UCC24610

www.ti.com

SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010

GATE Drive and R

GATE

Considerations

The GATE output driver is capable of sourcing >1-A peak current into the SR-MOSFET gate, and sinking >2 A

out of it. Standard low-inductance, low-loop-area design techniques should be employed to minimize stray

inductance which slows the MOSFET turn on and increases gate-drive ringing.

A series resistance R

GATE

from the GATE output to the MOSFET gate is used to damp this ringing, and its value

is chosen based on the standard critical damping formula for a series-LCR resonant tank.

(10)

where L

is the total series gate-loop inductance, C

iss

is the total effective input capacitance of the MOSFET, and

is the internal gate resistance of the MOSFET.

Please note that the total series resistance in the gate-drive path may also limit the peak GATE currents

obtainable below the rated capabilities of the device’s GATE output driver stage.

VCC Range and Bypassing Considerations

With a normal operating range of 4.5 V to 5.5 V, the device is well suited for 5-V nominal output applications and

can easily accommodate +/-10% transient VCC excursions due to system line and load disturbances. When the

average VCC voltage approaches the V

CC(off)

threshold (UVLO), system ripple and noise on VCC may cross that

threshold and shut down the controller unless adequate decoupling is provided from VCC to GND at the

controller pins.

High peak gate-drive currents during the GATE turn-on transition also require sufficient local capacitive

bypassing of the VCC pin to GND. For smaller SR-MOSFETs a minimum value of 0.1 mF may be sufficient, but

larger MOSFETs may require additional bypass capacitance to avoid excess ripple on the VCC voltage.

Suggested VCC bypass capacitance is 0.1 mF for each 2.2 nF of C

iss

Product Folder Link(s): UCC24610