Datasheet

SEC
PKG
VD
dI
L 0.3 V
dt
R
0.1A
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UCC24610
SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010 www.ti.com
Application Considerations
VD and VS Detection
VD and VS are differential inputs used to sense the voltage across the SR-MOSFET to determine when to turn
on and off the GATE output. When the GATE is off, the controller will not drive the GATE on until VD has
exceeded 1.5 V at least once and TOFF has expired. Once these two conditions are met, the controller is armed
to allow the GATE to turn on the next time the drain voltage falls 150 mV below the source voltage (VD - VS =
-150 mV). While the GATE is off, the SR-MOSFET may be blocking reverse current, or forward current may be
building up in the MOSFET body diode. Normally this body-diode current would generate about 700 mV forward
voltage drop (-700 mV
DS
), but when -150 mV is detected the GATE is turned on to enhance the MOSFET into a
synchronous rectifier. The GATE stays on for at least the minimum on time TON or longer until the SR-MOSFET
current diminishes to near zero. When the current reduces sufficiently such that the V
DS
voltage drop is only -5
mV, the GATE output is turned off. (It can be seen that the MOSFET R
DS(on)
determines the current level at
which the GATE is turned off, which then further factors into determining the Light-Load Mode inception point.) At
the same time, the controller is disarmed to prevent spurious GATE output. Because the MOSFET current is not
yet zero at GATE turn off, the V
DS
will briefly increase back up to the body-diode drop, however the additional
power loss is very small. The disarmed state of the controller prevents repeated turn on of the GATE (even
though V
DS
< -150 mV again). Once the current does decrease to zero, the drain voltage climbs past the 1.5-V
threshold, at which point the minimum off-time interval TOFF is triggered. Once V
DS
has exceeded 1.5 V and
TOFF has expired, the GATE circuit is re-armed to respond to the next turn-on condition.
Because the VD and VS inputs are connected across the SR-MOSFET body diode by way of its package leads,
the high secondary-side dI/dt through the lead inductances can impress excessive negative voltage on the VD
pin. This negative voltage can disrupt normal controller operation and prevent the device from switching. This
problem can be avoided by limiting the current drawn out of the VD pin to less than 100 mA. A resistor placed in
series between VD and the SR-MOSFET drain can be sized to provide the proper current limiting.
This resistor value is calculated by:
(1)
where L
PKG
is the total package inductance between the drain and source pads of the SR-MOSFET when
mounted on the PCB, and dI
SEC
/dt is the rate of rise of the secondary current after the primary-side switch turns
off. Include any stray trace inductance if the device GND pin is not connected directly to the SR-MOSFET source
pad.
The bias current of the VD pin through R
VD
(if any) generates a small offset voltage which can cause an apparent
shift in the SR-MOSFET turn-off threshold, leading to earlier turn off than desired, depending on the value of R
VD
.
To counter this offset voltage, a resistor of equal value can be placed in series with the VS pin to balance the
VD-VS comparator inputs (R
VS
= R
VD
).
Larger MOSFET packages such as TO-220 and TO-247 generally have significant internal inductances (on the
order of 10 nH ~ 20 nH), and are used in higher-power applications where dI/dt can be quite high. On the other
hand, low-power applications using smaller packages such as QFN style and even DPAK™ or equivalent
MOSFETs can have a sufficiently low L x dI/dt product such that R
VD
and R
VS
may not be necessary. Refer to
the MOSFET datasheet or consult with the manufacturer to determine the total inductance for the specific
MOSFET being considered for a synchronous-rectifier application.
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