Datasheet

GATE Output
TON Blanking
TOFF Blanking
ARMED
V
DS
> V
THARM
Detection
V
DS
> V
THOFF
Detection
V
DS
< V
THON
Detection
(A), (V)
V
DS
I
SEC
Turn-on Ringing
Resonant Ringing
V10093
(t)
UCC24610
SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010 www.ti.com
However, actual in-circuit waveforms are rarely as clean as shown in Figure 18. Instead, parasitic inductances
and capacitances set up resonant ringing at various inflection points in the waveforms. The UCC24610 has
control timing and programming options which helps avoid interference from such ringing with proper operation.
Figure 19 shows more realistic waveforms and the internal control timing which accommodates them. The
waveforms affecting the SR-MOSFET in a typical flyback circuit are shown.
Figure 19. Internal Signal Timing With Respect to Realistic DCM Waveforms
Minimum on-time TON is programmed with a resistor from TON, (pin 3) to GND to blank the response of the
turn-off detection circuit to prevent GATE from being turned-off from spurious crossings of V
TH(off)
due to noise
and ringing. TON is triggered by the GATE turning on. Refer to the TON programming section below for details.
Minimum off-time T
OFF
is programmed with a resistor from pin 2 to GND to blank the response of the turn-on
detection circuit to prevent GATE from being turned-on again from spurious crossings of V
TH(on)
due to excessive
C
OSS
resonant ringing. TOFF is triggered by V
DS
crossing V
THARM
after the GATE turns off. Refer to the TOFF
programming section below for details.
The GATE output may only turn on when the controller has been “armed” for the switching cycle. The controller
is armed for each successive SR cycle only after TOFF expires. Note that in high-frequency applications, an
excessively long TOFF may interfere with timely turn-on of GATE in the next switching cycle. GATE turn on will
be delayed if TOFF from the previous cycle has not yet expired.
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