Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power supply controllers/monitors 2.15 mA SOIC 8

UCC24610

GATEVD VS TON GNDEN/TOFF

SYNC VCC

+–

5 V

Out

8 5 7 3 2 6

UDG-10079

UDG-10096

UCC24610

GATEVD VS TON GNDEN/TOFF

SYNC

VCC

8 5 7 3 2 6

UCC24610

GATEVD VS TON GNDEN/TOFF

SYNC

VCC

8 5 7 3 2 6

5 V

12 V

OUT

BULK

UCC24610

www.ti.com

SLUSA87B –AUGUST 2010–REVISED SEPTEMBER 2010

GREEN Rectifier™ Controller Device

Check for Samples: UCC24610

FEATURES

DESCRIPTION

• Secondary-Side Controller Optimized for 5-V

This GREEN Rectifier™ controller is a

Systems

high-performance controller and driver for standard

and logic-level N-channel MOSFET power devices

• Up to 600-kHz Operating Frequency

used for low-voltage secondary-side synchronous

• V

MOSFET-Sensing

rectification.

• 1.6-Ω Sink, 2.0-Ω Source Gate-Drive

The combination of controller and MOSFET emulates

Impedances

a near-ideal diode rectifier. This solution not only

• Micro-Power Sleep Current for 90+ Designs

directly reduces power dissipation of the rectifier but

• Automatic Light-Load Management

also indirectly reduces primary-side losses as well,

due to compounding of efficiency gains.

• Synchronous Wake-Up From Sleep and

Light-Load Modes

Using drain-to-source voltage sensing, the

UCC24610 is ideal for Flyback and LLC-resonant

• Protection Features on Programming Inputs

power supplies but can also be used with other power

• SYNC Input for CCM Operation

architectures. The UCC24610 is optimized for output

• 20-ns Typical Turn-Off Propagation Delay

voltages from 4.5 V to 5.5 V, and is suitable for use

with lower and higher output voltages as well.

• Improved Efficiency and Design Flexibility

Over Traditional Diode Solution

The UCC24610 offers a programmable

• May Be Biased Directly From 5-V Output

false-triggering filter, a programmable timer to

automatically switch to Light-Load Mode at light load,

• Minimal Component Count

and a SYNC input for optional use in Continuous

Conduction Mode (CCM) systems. Protection

APPLICATIONS

features on TON and EN/TOFF pins prevent

• AC/DC 5-V Adapters

run-away on-time due to open-circuit or short-circuit

• 5-V Bias Supplies

fault conditions.

• Low Voltage Rectification Circuits

This device is available in an 8-pin SOIC package

• Flyback and LLC Converters

and an 8-pin, 3-mm x 3-mm QFN package with

PowerPad™.

LLC-Resonant Half Bridge

TYPICAL APPLICATIONS

Flyback Topology

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2GREEN Rectifier, PowerPad are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 GREEN Rectifier™ Controller Device Check for Samples: UCC24610 FEATURES DESCRIPTION • This GREEN Rectifier™ controller is a high-performance controller and driver for standard and logic-level N-channel MOSFET power devices used for low-voltage secondary-side synchronous rectification. 1 2 • • • • • • • • • • • • Secondary-Side Controller Optimized for 5-V Systems Up to 600-kHz Operating Frequency VDS MOSFET-Sensing 1.6-Ω Sink, 2.
PAGE 2
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 THERMAL INFORMATION UCC24610 THERMAL METRIC (1) Junction-to-ambient thermal resistance (2) qJA (3) qJCtop Junction-to-case (top) thermal resistance qJB Junction-to-board thermal resistance (4) qJCbot Junction-to-case (bottom) thermal resistance (5) (1) (2) (3) (4) (5) D DRB 8 PINS 8 PINS 147 67 89 84.6 82 20.3 UNITS °C/W 7.
PAGE 4
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS At VCC = 5 VDC, CGATE = 0 pF, RTON = 200 kΩ, REN/TOFF = 100 kΩ, −40°C < TJ = TA < 125°C, all voltages are with respect to GND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Bias Supply ICCSTART VCC current, undervoltage ICCSTBY VCC current, disabled VCC = 5.
PAGE 5
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) At VCC = 5 VDC, CGATE = 0 pF, RTON = 200 kΩ, REN/TOFF = 100 kΩ, −40°C < TJ = TA < 125°C, all voltages are with respect to GND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Minimum Off-Time Setting TOFFLR Minimum off-time, low resistance REN/TOFF = 100 kΩ 4.94 7.
PAGE 6
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com DEVICE INFORMATION SOIC 8-Pin (D) QFN-8 (DRB) SYNC 1 8 VD SYNC 1 8 VD EN/TOFF 2 7 VS EN/TOFF 2 7 VS TON 3 6 GND TON 3 6 GND VCC 4 5 GATE VCC 4 5 GATE Functional Block DIagram VCC 4 Sleep-Mode & Wake-Up Synchronization 10 μA UVLO 10 μA EN/TOFF 2 + 1.4 V/0.8 V VD 8 Q ... S + R 5 mV REFs Minimum Off-Time 1.
PAGE 7
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 TERMINAL FUNCTIONS TERMINAL NAME EN/TOFF GATE GND PowerPad™ SYNC TON NO. 2 5 I/O DESCRIPTION I EN/TOFF (Combined Enable Function & Programmable Off-Time Timer) When VCC falls below the VCC(off) threshold, the UCC24610 is in UVLO Mode, the EN/TOFF input is internally connected to GND through a 10-kΩ resistance and the internal current source is turned off.
PAGE 8
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME VCC NO. 4 I/O DESCRIPTION I VCC (Positive Power Input) Connect a DC power voltage to VCC. Bypass VCC to GND with a 0.1-µF or larger ceramic capacitor using short PC board tracks. VCC supplies power to all circuits in the UCC24610. Under-Voltage Lockout (UVLO) comparators prevent operation until VCC rises above VCC(on).
PAGE 9
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 MODES OF OPERATION UVLO Mode When the VCC voltage to the device has not yet reached the VCC(on) threshold, or has fallen below the UVLO threshold VCC(off), the device operates in the low-power UVLO Mode. In this mode, most internal functions are disabled and ICC current is typically much less than 100 µA.
PAGE 10
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE THRESHOLD VOLTAGE vs TEMPERATURE 4.6 10,000 No Gate Switching EN > 1.6 VVCC - Threshold Voltage - V IVCC - Bias Supply Current - mA 4.5 1,000 EN < 0.7 100 10 VCCON 4.4 4.3 VCCOFF 4.2 1 4.1 4.0 0 0 1 3 2 4 5 6 -50 7 -25 0 75 100 Figure 1. Figure 2.
PAGE 11
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) ENABLE CURRENT vs TEMPERATURE THRESHOLD VOLTAGE vs TEMPERATURE 1.6 -9.3 VENON EN > 1.6 V 1.4 VEN - Threshold Voltage - V IEN-ON - Enable Current - mA -9.5 -9.7 -9.9 -10.1 -10.3 -10.5 1.2 1.0 VENOFF 0.8 0.6 0.4 0.2 -10.7 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 TJ - Temperature - °C 50 75 100 125 150 125 150 TJ - Temperature - °C Figure 5. Figure 6.
PAGE 12
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VDS GATE-OFF THRESHOLD VOLTAGES vs TEMPERATURE VDS GATE-ON THRESHOLD VOLTAGE vs TEMPERATURE -2 -0.10 VS = +0.1 V -0.11 VS = -0.1 V -3 -0.13 -4 VTHON - Voltage - V VTHOFF - Voltage - mV -0.12 -5 -6 VS = 0 V -0.14 -0.15 -0.16 -0.17 -0.18 -7 -0.19 -8 -0.
PAGE 13
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) MINIMUM OFF TIME vs TOFF RESISTANCE 5.0 10 4.5 9 4.0 8 TOFF - Minimum OFF Time - ms TON - Minimum ON Time - ms MINIMUM ON TIME vs TON RESISTANCE 3.5 3.0 2.5 2.0 1.5 1.0 0.5 7 6 5 4 3 2 1 0 0 0 0.10 0.05 0.15 0.20 0.25 0.30 0 0.10 0.05 RTON - TON Resistance - MW 0.20 0.15 0.25 0.30 0.35 REN/TOFF - TOFF Resistance - MW Figure 13. Figure 14.
PAGE 14
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION Normal Operation The UCC24610 GREEN Rectifier™ Synchronous-Rectifier (SR) controller powers up into UVLO Mode as VCC increases from zero volts. Enable Current (IEN) from the EN/TOFF pin is inhibited until VCC exceeds the VCC(on) threshold, and remains active as long as VCC exceeds the VCC(off) threshold. The voltage on the EN/TOFF pin determines whether the controller is Enabled or not.
PAGE 15
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 The UCC24610 SR controller determines the conduction time of the SR-MOSFET by comparing the MOSFET’s drain-to-source voltage against a turn-on threshold and a turn-off threshold. The GATE output is driven High when VDS of the MOSFET exceeds VTH(on) and is driven Low when VDS decreases below VTH(off) as illustrated in Figure 18.
PAGE 16
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com However, actual in-circuit waveforms are rarely as clean as shown in Figure 18. Instead, parasitic inductances and capacitances set up resonant ringing at various inflection points in the waveforms. The UCC24610 has control timing and programming options which helps avoid interference from such ringing with proper operation. Figure 19 shows more realistic waveforms and the internal control timing which accommodates them.
PAGE 17
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 Light-Load Operation During normal operation, the synchronous rectifier conduction time is longer than the programmed minimum on-time. If load current decreases enough that the SR conduction time becomes shorter than the programmed minimum on-time, a light-load condition is detected. The light-load latch is set and the next GATE output pulse is blanked, so only the body diode of the controlled MOSFET conducts.
PAGE 18
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Application Considerations VD and VS Detection VD and VS are differential inputs used to sense the voltage across the SR-MOSFET to determine when to turn on and off the GATE output. When the GATE is off, the controller will not drive the GATE on until VD has exceeded 1.5 V at least once and TOFF has expired.
PAGE 19
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 Enabling and TOFF Programming The controller must be out of UVLO Mode, or the internal current source on EN/TOFF pin is shut off and the pin is pulled low with an internal 10-kΩ resistor. Before the device is in the Enabled state, the current source on EN/TOFF delivers 20 mA. Prudent design practice indicates that a minimum REN/TOFF value of 93 kΩ is necessary to ensure the pin voltage exceeds the disable threshold.
PAGE 20
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TON Programming The voltage on this pin is internally regulated to 2 V, and an external resistor to GND sets a current which programs the minimum on time TON. If a noise-filter capacitor is deemed to be necessary on this pin, do not exceed 100 pF to avoid instability of the 2-V regulator.
PAGE 21
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 GATE Drive and RGATE Considerations The GATE output driver is capable of sourcing >1-A peak current into the SR-MOSFET gate, and sinking >2 A out of it. Standard low-inductance, low-loop-area design techniques should be employed to minimize stray inductance which slows the MOSFET turn on and increases gate-drive ringing.
PAGE 22
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com SYNC Input Considerations In applications where the synchronous rectifier is used in Continuous Conduction Mode (CCM) such as CCM-Flyback and LLC converters, it is imperative that the SR-MOSFET be turned off as soon as the primary-side switch turns on, to prevent reverse conduction of the SR-MOSFET.
PAGE 23
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 CSYNC is the synchronization signal coupling capacitor, rated to cross the primary-to-secondary isolation boundary. It is used to couple a negative-going voltage into the UCC24610 SYNC input (pin 1) to turn off the GATE output to the SR-MOSFET when the primary-side MOSFET is turned on. RSYNC is an optional external current-limiting resistor used to reduce the peak current into the SYNC input.
PAGE 24
UCC24610 SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com 2. After the ΔVDS_PRI Transition After the ΔVDS_PRI transition, the SYNC signal will begin to reset back to VCC by charging exponentially. This allows the value of the SYNC coupling capacitor CSYNC to be determined by: CSYNC = 1.5 ´ tMIN RSYNC + rSYNC (13) The value of CSYNC is chosen to ensure that the SYNC signal stays below the SYNC threshold for at least 20 ns.
PAGE 25
UCC24610 www.ti.com SLUSA87B – AUGUST 2010 – REVISED SEPTEMBER 2010 6. The CSYNC Capacitor Resets The CSYNC capacitor resets during the off-time of the primary-side MOSFET, while the SR-FET is conducting. The reset current iSYNC_RESET is similar to iSYNC. However, this reset current flows through the internal diode between SYNC and VCC pins of the device.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC24610DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC24610DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 UCC24610DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.
PAGE 29
PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC24610DR SOIC D 8 2500 340.5 338.1 20.6 UCC24610DRBR SON DRB 8 3000 370.0 355.0 55.0 UCC24610DRBT SON DRB 8 250 220.0 205.0 50.
PAGE 30
PAGE 31
PAGE 32
PAGE 33
PAGE 34
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.