Datasheet

6
UC2855A/B
UC3855A/B
VAO: This is the output of the voltage amplifier. At a
given input RMS voltage, the voltage on this pin will vary
directly with the output load. The output swing is limited
from approximately 100mV to 6V. Voltage levels below
1.5V on this pin will inhibit the multiplier output.
VCC: Positive supply rail for the IC. Bypass this pin to
GND with a 1µF low ESL, ESR ceramic capacitor. This
pin is internally clamped to 20V. Current into this clamp
should be limited to less than 10mA. The UC3855A has a
15.5V (nominal) turn on threshold with 6 volts of hyster
-
esis while the UC3855B turns on at 10.5V with 500mV of
hysteresis.
VRMS: This pin is the feedforward line voltage compen
-
sation input to the multiplier. A voltage on VRMS propor
-
tional to the AC input RMS voltage commands the
multiplier to alter the current command signal by
1/VRMS
2
to maintain a constant power balance. The in
-
put to VRMS is generally derived from a two pole low
pass filter/voltage divider connected to the rectified AC
input voltage. This feature allows universal input supply
voltage operation and faster response to input line fluc-
tuations for the PFC boost preregulator. For most de-
signs, a voltage level of 1.5V on this pin should
correspond to low line, and 4.7V for high line. The input
range for this pin extends from 0 to 5.5V.
VSENSE: This pin is the inverting input of the voltage
amplifier and serves as the output voltage feedback point
for the PFC boost converter. It senses the output voltage
through a voltage divider which produces a nominal 3V.
The voltage loop compensation is normally connected
between this pin and VAO. The VSENSE pin must be
above 1.5V at 25°C, (1.9V at –55°C) for the current syn
-
thesizer to work properly.
ZVS: This pin senses when the drain voltage of the main
MOSFET switch has reached approximately zero volts,
and resets the ZVT latch via the ZVT comparator. A mini
-
mum and maximum ZVTOUT pulse width are program
-
mable from this pin. To directly sense the ≈400V drain
voltage of the main switch, a blocking diode is connected
between ZVS and the high voltage drain. When the drain
reaches 0V, the level on ZVS is ≈0.7V which is below the
2.6V ZVT comparator threshold. The maximum ZVTOUT
pulse width is approximately equal to the oscillator blank
-
ing period time.
ZVTOUT: The output of the ZVT block is a 750mA peak
totem pole MOSFET gate driver on ZVTOUT. Since the
ZVT MOSFET switch is typically 3X smaller than the
main switch, less peak current is required from this out-
put. Like GTOUT, a series gate resistor and Schottky di-
ode to GND are recommended. This pin may also be
used as a high current synchronization output driver.
PIN DESCRIPTIONS (cont.)
For more information see Unitrode Applications Note U-153.
Frequency
kHz
Phase
Margin
degrees
Open-Loop
Gain
dB
-20
0
20
40
60
80
100
120
0.1 1 10 100 1000 10000
Figure 2. Voltage Amplifier Gain Phase vs Frequency
log f
Gain (dB)
-60
-40
-20
0
20
40
60
0
80
-45
Phase
Degrees
100
-90
120
10kHz 1MHz 10MHz
100kHz
Gain
Phase
5.992 496 516 MHz
Figure 1. Current Amplifier Frequency Response