Datasheet

DETAILED BLOCK DIAGRAM
COMP: COMP is the output of the error amplifier and the
input of the PWM comparator. To limit PWM on-time, this
pin is clamped to approximately 10V. To implement soft
start, the COMP pin can be pulled low and ramped up with
a PNP transistor, a capacitor, and a resistor.
GND: Ground for all functions is through this pin.
ISET: The dominant function is of this pin is to program
RAMP charging current. RAMP charging current is
approximately 5V divided by the external resistor placed
from ISET to ground. Resistors in the range of 10kΩ to
50kΩ are recommended, producing currents in the range
of 100µA to 500µA.
A second function of ISET is as reference output. The ISET
pin is normally regulated to 5V ±10%. It is critical that this
pin only see the loading of the RAMP programming resistor,
but a high input-impedance comparator or amplifier may be
connected to this pin or to a tap on the RAMP programming
resistor if required.
The third function of the ISET pin is as a FAULT output. In
the event of an over-current fault, the ISET pin is forced to
approximately 9V by the fault comparator. This can be used
to trip an external protection circuit which can disable the
load or start a fault restart cycle.
ISNS: This input to the zero and over current comparators
is specially built to allow operation over a ±5V dynamic
range. In noisy systems or systems with very high Q
inductors, it is desirable to filter the signal entering the ISNS
input to prevent premature restart or fault cycles. For best
accuracy, ISNS should be connected to a current sense
resistor through no more than 200 ohms.
OUT: The output of a high-current power driver capable of
driving the gate of a power MOSFET with peak currents
exceeding ±500mA. To prevent damage to the power
MOSFET, the OUT pin is internally driven by a 12V supply.
However, lead inductance between the OUT pin and the
load can cause overshoot and ringing. External current
boost transistors will increase this overshoot and ringing. If
there is any significant distance between the IC and the
MOSFET, external clamp diodes and/or series damping
resistors may be required. OUT is actively held low when
the VCC is below the UVLO threshold.
RAMP: A controlled on-time PWM requires a timer whose
time can be modulated by an external voltage. The timer
current is programmed by a resistor from ISET to GND. A
capacitor from RAMP to GND sets the on time in
conjunction with the voltage on COMP. Recommended
values for the timer capacitors are between 100pF and 1nF.
VCC: VCC is the logic and control power connection for this
device. VCC current is the sum of active device supply
current and the average OUT current. Knowing the
maximum operating frequency and the MOSFET gate
charge (Qg), average OUT current can be estimated by:
I
OUT
= Q
g
× F
To prevent noise problems, bypass VCC to GND with both
a ceramic and an electrolytic capacitor.
VFB: VFB is the error amplifier inverting input. This input
serves as both the voltage sense input to the error amplifier
UC1852
UC2852
UC3852
PIN DESCRIPTIONS
UDG-92003
3