Datasheet

3
UC1706
UC2706
UC3706
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1706, –25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; V
IN = VC = 20V. TA =TJ.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNITS
Output High Sat., V
C-VO IO = -50mA 2.0 V
Output Low Sat., V
O IO = 50mA 0.4 V
I
O = 500mA 2.5 V
Inhibit Threshold V
REF = 0.5V 0.4 0.6 V
V
REF = 3.5V 3.3 3.7 V
Inhibit Input Current V
REF = 0 –10 –20 µA
Analog Threshold V
CM = 0 to 15V, for the UC2706 and UC3706 100 130 160 mV
V
CM = 0 to 15V, for the UC1706 80 130 160 mV
Input Bias Current V
CM = 0 –10 –20 µA
Thermal Shutdown 155 °C
TYPICAL SWITCHING CHARACTERISTICS: VIN = VC = 20V, TA = 25°C. Delays measured to 10% output change.
PARAMETERS TEST CONDITIONS OUTPUT C
L = UNITS
From Inv. Input to Output:
open 1.0 2.2 nF
Rise Time Delay 110 130 140 ns
10% to 90% Rise 20 40 60 ns
Fall Time Delay 80 90 110 ns
90% to 10% Fall 25 30 50 ns
From N. I. Input to Output:
Rise Time Delay 120 130 140 ns
10% to 90% Rise 20 40 60 ns
Fall Time Delay 100 120 130 ns
90% to 10% Fall 25 30 50 ns
V
C Cross-Conduction Current Spike Duration Output Rise 25 ns
Output Fall 0 ns
Inhibit Delay Inhibit Ref. = 1V, Inhibit Inv. = 0.5 to 1.5V 250 ns
Analog Shutdown Delay Stop Non-Inv. = 0V, Stop Inv. = 0 to 0.5V 180 ns
CIRCUIT DESCRIPTION
Outputs
The totem-pole outputs have been designed to minimize
cross-conduction current spikes while maximizing fast,
high-current rise and fall times. Current limiting can be
done externally either at the outputs or at the common
V
C pin. The output diodes included have slow recovery
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Flip/Flop
Grounding pin 7 activates the internal flip-flop to alter
-
nate the two outputs. With pin 7 open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at last 200nsec must be pro
-
vided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the “OFF” state is de
-
fined as the outputs low.
Digital Inputs
With both an inverting and non-inverting input available,
either active-high or active-low signals may be accepted.
These are true TTL compatible inputs—the threshold is
approximately 1.2V with no hysteresis; and external pull-
up resistors are not required.
Inhibit Circuit
Although it may have other uses, this circuit is included to
eliminate the need for deadband control when driving
relatively slow bipolar power transistors. A diode from
each inhibit input to the opposite power switch collector
will keep one output from turning-on until the other has
turned-off. The threshold is determined by the voltage on
pin 15 which can be set from 0.5 to 3.5V. When this cir
-
cuit is not used, ground pin 15 and leave 1 and 16 open.