Datasheet

UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
7
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The share loop compensation capacitor, C
C
is calculated to produce the desired share loop unity gain crossover
frequency, f
C
. The share loop error amplifier’s transconductance, g
M
is nominally 4.5 ms. The values of the
resistors are already known. Typically, f
C
is set to at least one order of magnitude below the converter’s closed
loop bandwidth. The load share circuit is primarily intended to compensate for each converter’s initial output
voltage tolerance and temperature drift, not for differences in their transient response. The term A
PWR(fc)
is the
gain of the power supply measured at the desired share loop crossover frequency, f
C
. This gain can be
measured by injecting the measurement signal between the positive output and the positive sense terminal of
the power supply.
Step 5.
R
C
+
1
2p f
C
C
C
A resistor in series with C
C
is required to boost the phase margin of the load share loop. The zero is placed at
the load share loop crossover frequency, f
C
.
When the system is powered up, the converter with the highest output voltage tends to source the most current
and take control of the share bus. The other converters increase their output voltages until their output currents
are proportional to the share bus voltage minus 50 mV. The converter which in functioning as the master may
change due to warmup drift and differences in load and line transient response of each converter.
ADDITIONAL INFORMATION
Please refer to the following topic for additional application information.
1. Application Note U−163, (TI Literature No. SLUA128) The UC3902 Load Share Controller and Its
Performance in Distributed Power Systems by Laszlo Balogh
(6)