Datasheet

G +
DV
COMP
DV
CS)
; DV
CS
* + 0 V 1 V.
(4) Amplifier gain defined as:
UC2856Q
SGLS265A –NOVEMBER 2004– REVISED MAY 2011 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T
A
= –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and T
A
= T
J
(unless otherwise stated)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER SECTION
Input offset voltage V
CM
= 2 V 5 mV
Input bias current –1 µA
Input offset current 500 nA
Common mode range VIN = 8 V to 40 V 0 VIN–2 V
Open loop gain V
O
= 1.2 V to 3 V 80 100 dB
Unity gain bandwidth T
J
= 25°C 1 1.5 MHz
CMRR V
CM
= 0 V to 38 V, VIN = 40 V 75 100 dB
PSRR VIN = 8 V to 40 V 80 100 dB
Output sink current V
ID
= -15 mV V
COMP
= 1.2 V 5 10 mA
Output source current V
ID
= 15 mV V
COMP
= 2.5 V –0.4 –0.5 mA
High-level output voltage V
ID
= 50 mV, R
L
(COMP) = 15 kΩ 4.3 4.6 4.9 V
Low-level output voltage V
ID
= –50 mV, R
L
(COMP) = 15 kΩ 0.7 1 V
CURRENT SENSE AMPLIFIER SECTION
Amplifier gain V
CS–
= 0 V, CL SS Open
(3) (4)
2.5 2.75 3 V/V
Maximum differential input signal (V
CS+
– V
CS–
) CL SS Open 3, R
L
(COMP) = 15 kΩ 1.1 1.2 V
Input offset voltage V
CL SS
= 0.5 V COMP open
(3)
5 35 mV
CMRR V
CM
= 0 V to 3 V 60 dB
PSRR VIN = 8 V to 40 V 60 dB
Input bias current V
CL SS
= 0.5 V, COMP open
(3)
–1 µA
Input offset current V
CL SS
= 0.5 V, COMP open
(3)
1 mA
Input common mode range 0 3 V
Delay to outputs V
EA+
= VREF, EA– = 0 V, CS+ – CS– = 0 V to 1.5 V 120 250 ns
CURRENT LIMIT ADJUST SECTION
Current limit offset V
CS–
= 0 V, V
CS+
= 0 V, COMP Open
(3)
0.4 0.5 0.6 V
Input bias current V
EA+
= VREF, V
EA–
= 0 V –10 –30 µA
SHUTDOWN TERMINAL SECTION
Threshold voltage 0.95 1.00 1.05 V
Input voltage range 0 5 V
Minimum latching current (I
CL SS
)
(5)
3 1.5 mA
Maximum non-latching current (I
CL SS
)
(6)
1.5 0.8 mA
Delay to outputs V
SHUTDOWN
= 0 V to 1.3 V 65 110 ns
OUTPUT SECTION
Collector-emitter voltage 40 V
Off-state bias current VC = 40 V 250 µA
I
OUT
= 20 mA 0.1 0.5
Output low level voltage V
I
OUT
= 200 mA 0.5 2.6
I
OUT
= –20 mA 12.5 13.2
Output high level voltage V
I
OUT
= –200 mA 12 13.1
Rise time C1 = 1 nF 40 80 ns
Fall time C1 = 1 nF 40 80 ns
UVLO low saturation VIN = 0 V, I
OUT
= 20 mA 0.8 1.5 V
(3) Parameter measured at trip point of latch with VEA+ = VREF, VEA- = 0 V.
(5) Current into CL SS assured to latch circuit into shutdown state.
(6) Current into CL SS assured not to latch circuit into shutdown state.
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