Datasheet

t
LEB
+ 0.5
ǒ
R ø 10 kW
Ǔ
C
(2)
UDG−95105
C
T
CLK/LEB
LEB
RAMP
Input
Blanked
RAMP
to PWM
UC2825A-EP
SGLS305D JULY 2005REVISED SEPTEMBER 2010
www.ti.com
Leading-Edge Blanking (LEB)
The UC2825A-EP performs fixed-frequency PWM control. The UC2825A-EP outputs are alternately controlled.
During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying
in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is
controlled by the PWM comparator, current-limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error-amplifier output) and terminates
the pulse. LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse.
This allows noise inherent with switched-mode power conversion to be rejected. The PWM ramp input may not
require any filtering as a result of LEB.
To program an LEB period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal
10-k resistor determines the blanked interval. The 10-k resistor has a 10% tolerance. For more accuracy, an
external 2-k 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 k with a tolerance of
2.4%. The design equation is:
Values of R less than 2 k should not be used.
LEB also is applied to the current-limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the
pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent
faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set, and the outputs are
driven low. For this reason, some noise filtering may be required on the ILIM pin.
Figure 4. LEB Operational Waveforms
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