Datasheet

1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
DW PACKAGE
(TOP VIEW)
UC2825A-EP
www.ti.com SGLS305D –JULY 2005–REVISED SEPTEMBER 2010
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
CLK/LEB 4 O Clock/leading-edge blanking. Output of the internal oscillator.
Capacitor timing. Timing capacitor connection for oscillator frequency programming. The timing capacitor
CT 6 I
should be connected to the device ground using minimal trace length.
EAOUT 3 O Output of the error amplifier for compensation
GND 10 Analog ground return
ILIM 9 I Input to the current-limit comparator
INV 1 I Inverting input to the error amplifier
NI 2 I Noninverting input to the error amplifier
OUTA 11 O High-current totem-pole output A of the on-chip drive stage
OUTB 14 O High-current totem-pole output B of the on-chip drive stage
PGND 12 Ground return for the output driver stage
Noninverting input to the PWM comparator, with 1.25-V internal input offset. In voltage-mode operation, this
RAMP 7 I serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation,
this serves as the slope compensation input.
RT 5 I Resistor timing. Timing resistor connection for oscillator frequency programming.
SS 8 I Soft-start. SS also doubles as the maximum duty cycle clamp.
Power-supply for the output stage. This pin should be bypassed with a 0.1-mF monolithic ceramic low-ESL
VC 13
capacitor with minimal trace lengths.
Power supply for the device. This pin should be bypassed with a 0.1-mF monolithic ceramic low-ESL
VCC 15 O
capacitor with minimal trace lengths.
5.1-V reference. For stability, the reference should be bypassed with a 0.1-mF monolithic ceramic low-ESL
VREF 16
capacitor and minimal trace length to the ground plane.
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