Datasheet

UDG−95115
C
T
V
REF
GND
V
C
V
CC
OUT
P
GND
To Analog
Circuitry
Signal Ground
Power Ground
V
CC
C
BULK
Power
Stage
VIN
RTN
UC2825A-EP
www.ti.com SGLS305D –JULY 2005–REVISED SEPTEMBER 2010
Ground Planes
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct
operation of the chip. A ground plane must be employed. A unique section of the ground plane must be
designated for high di/dt currents associated with the output stages. This point is the power ground to which the
PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a
single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC
should be bypassed directly to power ground with a good high-frequency capacitor. The sources of the power
MOSFET should connect to power ground as should the return connection for input power to the system and the
bulk input capacitor. The output should be clamped with a high-current Schottky diode to both VCC and PGND.
Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high-frequency
capacitor. Low-ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog
circuitry likewise, should be bypassed to the signal ground plane.
Figure 13. Ground Planes
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