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UC1824 Printed Circuit Board Layout Considerations
UC1824
UC2824
UC3824
SLUS326A – MARCH 1997 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for, R
T
= 3.65k, C
T
= 1 nF, V
CC
= 15 V, –55 ° C < T
A
< 125 ° C for the
UC1824, –40 ° C < T
A
< 85 ° C for the UC2824, and 0 ° C < T
A
< 70 ° C for the UC3824, T
A
= T
J
.
UC1824
UC3824
UC2824
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Current limit threshold 0.9 1 1.1 0.9 1 1.1
V
Shutdown threshold 1.25 1.40 1.55 1.25 1.40 1.55
Delay to output 50 80 50 80 ns
Output Section
I
OUT
= 20 mA 0.25 0.40 0.25 0.40
Output low level
I
OUT
= 200 mA 1.2 2.2 1.2 2.2
V
I
OUT
= –20 mA 13 13.5 13 13.5
Output high level
I
OUT
= –200 mA 12 13 12 13
Collector leakage V
C
= 30 V 100 500 10 500 μ A
Rise/fall time
(2)
CL = 1 nF 30 60 30 60 ns
Under-Voltage Lockout Section
Start threshold 8.8 9.2 9.6 8.8 9.2 9.6
V
UVLO hysteresis 0.4 0.8 1.2 0.4 0.8 1.2
Supply Current Section
Start up current V
CC
= 8 V 1.1 2.5 1.1 2.5
mA
ICC V
PIN 1
, V
PIN 7
, V
PIN 9
= 0 V; V
PIN 2
= 1 V 22 33 22 33
(2) This parameter not 100% tested in production but guaranteed by design.
High speed circuits demand careful attention to layout and component placement. To assure proper
performance of the UC1824 follow these rules:
1. Use a ground plane.
2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output
pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves
this purpose.
3. Bypass V
CC
, V
C
, and V
REF
. Use 0.1- μ F monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the
ground plane.
4. Treat the timing capacitor, C
T
, like a bypass capacitor.
5
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