Datasheet

UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
9
www.ti.com
APPLICATION INFORMATION
PCB LAYOUT CONSIDERATIONS
High speed circuits demand careful attention to layout and component placement. To assure proper
performance of the UC2802x follow these rules:
1. Use a ground plane.
2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output
pins to ring below ground. A series gate r esistor or a shunt 1-A Schottky diode at the output pin serves this
purpose.
3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the
ground plane.
4. Treat the timing capacitor, C
T
, as a bypass c apacitor.
ERROR AMPLIFIER
Figure 2 shows a simplified schematic of the UC2802x error amplifier and Figures 3 and 4 show its
characteristics.
UDG--03049
200 Ω
INV
NI
VREF
EAOUT
2
1
16
3
5.1 V
Figure 2. Simplified Error Amplifier Schematic