Datasheet

UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
7
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TERMINAL FUNCTIONS
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UC28023 UC28025
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O DESCRIPTION
CLOCK 4 4 O Output of the internal oscillator
CT 6 6 I
Timing capacitor connection pin for oscillator f requency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
EAOUT 3 3 O Output of the error amplifier for compensation
GND 10 10 -- Analog ground return pin.
ILIM/SD 9 9 I Input to the current limit comparator and the shutdown comparator.
ILIMREF 11 -- I Pin to set the current limit threshold externally.
INV 1 1 I Inverting input to the error amplifier
NI 2 2 I Non-inverting input to the error amplifier
OUT 14 -- O High current totem pole output of the on-chip drive stage.
OUTA -- 11 O High current totem pole output A of the on-chip drive stage.
OUTB -- 14 O High current totem pole output B of the on-chip drive stage.
PGND 12 12 -- Ground return pin for the output driver stage
RAMP 7 7 I
Non-inverting input to the PWM comparator with 1.25 -V internal input offset. In voltage mode
operation this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RT 5 5 I Timing resistor connection pin for oscillator frequency programming
SS 8 8 I Soft-start input pin.
VC 13 13 --
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor with minimal trace lengths.
VCC 15 15 --
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths
VREF 16 16 O
5.1--V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic c eramic
low ESL capacitor and minimal trace length to the ground plane.