Datasheet

TXS0102
SCES640D –JANUARY 2007– REVISED MARCH 2011 www.ti.com
Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or
push-pull) drivers that are interfaced to the TXS0102 I/O pins. Since the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup
resistors.
The fall time (t
fA
, t
fB
) of a signal depends on the edge-rate and output impedance of the external device driving
TXS0102 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the t
PHL
and max data rates also depend on the output impedance of the external driver. The values for
t
fA
, t
fB
, t
PHL
, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic I
CC
,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXS0102 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level
affects.
Power Up
During operation, ensure that V
CCA
≤ V
CCB
at all times. The sequencing of each power supply will not damage
the device during the power up operation, so either power supply can be ramped up first.
Enable and Disable
The TXS0102 has an OE input that is used to disable the device by setting OE low, which places all I/Os in the
Hi-Z state. The disable time (t
dis
) indicates the delay between the time when OE goes low and when the outputs
are disabled (Hi-Z). The enable time (t
en
) indicates the amount of time the user must allow for the one-shot
circuitry to become operational after OE is taken high.
Pullup or Pulldown Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to V
CCA
, and each B-port I/O has an internal 10-kΩ pullup
resistor to V
CCB
. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O
to V
CCA
or V
CCB
(in parallel with the internal 10-kΩ resistors). Adding lower value pull-up resistors will effect V
OL
levels, however. The internal pull-ups of the TXS0102 are disabled when the OE pin is low.
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