Datasheet
TX810
SLLS996A –SEPTEMBER 2009–REVISED APRIL 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
TRANSPORT MEDIA, OPERATING TEMPERATURE
PACKAGED DEVICES PACKAGE TYPE
QUANTITY RANGE
TX810IRHHT Tape and Reel, 250
S-PVQFN-N36 0~70°C
TX810IRHHR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Supply Voltage, VD -0.3 ~ +6 V
Supply Voltage, VP -0.3 ~ +6 V
Supply Voltage, VN -6 ~ +0.3 V
Supply Voltage, VB -0.3 ~ +6 V
Input AC voltage, INn ±100 V
Input at Vsub -6 ~ +0.3 V
Output current, I
O
15 mA
Maximum junction temperature, continuous operation, long term reliability
(2)
T
J
125°C
Storage temperature range, T
stg
-55°C to 150°C
HBM 500 V
ESD ratings CDM 750 V
MM 200 V
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
TX810
THERMAL METRIC
(1)
RHH UNITS
(OLFM Airflow Assumed)
36 PINS
q
JA
Junction-to-ambient thermal resistance
(2)
29.7
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
27
q
JB
Junction-to-board thermal resistance
(4)
7.2 °C/W
y
JT
Junction-to-top characterization parameter
(5)
0.1
y
JB
Junction-to-board characterization parameter
(6)
7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
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