Datasheet

AUD_DIR
AUDIO_CLK(A)
AUDIO_CLK(B)
AUDIO_FSYNC(A)
AUDIO_F_SYNC(B)
V
CCB
SDIO-CLK(B)
SDIO-CLK(A)
WLAN-ENABLE(B)
WLAN-ENABLE(A)
WLAN-IRQ(B)
WLAN-IRQ(A)
CLK-REQ(B)
CLK-REQ(A)
V
CCA
OE
SLOW_CLK(A) SLOW_CLK(B)
AUDIO_OUT(A) AUDIO_OUT(B)
AUDIO_IN(A) AUDIO_IN(B)
BT_EANBLE(A) BT_EANBLE(B)
BT_UART_RX(A) BT_UART_RX(B)
BT_UART_CTS(A) BT_UART_CTS(B)
BT_UART_TX(A) BT_UART_TX(B)
BT_UART_RTS(A) BT_UART_RTS(B)
Control
Logic
V
CCA
V
CCB
Gate Control
One-Shot
One-Shot
Translator
SDIO-CMD(A) SDIO-CMD(B)
R
(see Note A)
1
R
(see Note A)
2
One-Shot
One-Shot
Translator
V
CCA
V
CCB
Gate Control
One-Shot
One-Shot
Translator
SDIO-DATA0(A) SDIO- (B)DATA0
R
(see Note A)
1
R
(see Note A)
2
One-Shot
One-Shot
Translator
V
CCA
V
CCB
Gate Control
One-Shot
One-Shot
Translator
SDIO- (A)DATA1 SDIO- (B)DATA1
R
(see Note A)
1
R
(see Note A)
2
One-Shot
One-Shot
Translator
V
CCA
V
CCB
Gate Control
One-Shot
One-Shot
Translator
SDIO- (A)DATA2 SDIO- (B)DATA2
R
(see Note A)
1
R
(see Note A)
2
One-Shot
One-Shot
Translator
V
CCA
V
CCB
Gate Control
One-Shot
One-Shot
Translator
SDIO- (A)DATA3 SDIO- (B)DATA3
R
(see Note A)
1
R
(see Note A)
2
One-Shot
One-Shot
Translator
Audio
Control
SDIO Bit
SDIO Bit
SDIO Bit
SDIO Bit
SDIO Bit
TWL1200
SCES786A –JUNE 2009–REVISED NOVEMBER 2009 www.ti.com
LOGIC DIAGRAM
A. R
1
and R
2
resistor values are determined based upon the logic level applied to the A port or B port as follows:
R
1
and R
2
= 25 kΩ when a logic level low is applied to the A port or B port.
R
1
and R
2
= 4 kΩ when a logic level high is applied to the A port or B port.
R
1
and R
2
= 70 kΩ when the port is deselected (or in High-Z or 3-state).
B. OE controls all output buffers. When OE = high, all outputs are Hi-Z.
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