Datasheet

TWL1200
SCES786A –JUNE 2009–REVISED NOVEMBER 2009 www.ti.com
For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.
The V
GATE
gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance
from a control signal.
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,
helping maintain the data rate through the device.
During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T
1
, T
3
) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during
the low-to-high transition to speed up the rising-edge signal.
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T
2
, T
4
) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first.
To minimize dynamic I
CC
and the possibility of signal contention, the user should wait for the O.S. circuit to
turn-off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum
pulse-width number provided in the Timing Requirements section of this data sheet.
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or
both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the
pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change
value based on whether a Low or a High is being passed through the SDIO lines, as follows:
• R
PU1
and R
PU2
values are 25 kΩ when the output is driving a low
• R
PU1
and R
PU2
values are 4 kΩ when the output is driving a high
• R
PU1
and R
PU2
values are 70 kΩ when the device is disabled via the OE pin or by pulling the either V
CCA
or
V
CCB
to 0 V.
The reason for using these "smart" pullup resistors is to allow the TWL1200 to realize a lower static power
consumption (when the I/Os are low), support lower V
OL
values for the same size pass-gate transistor, and
improved simultaneous switching performance.
Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level driver interfaced to the
SDIO pins. Since the high bandwidth of these bidirectional SDIO circuits necessitates the need for a port to
quickly change from an input to an output (and vice-vera), they have a modest dc-current "sourcing" capability of
hundreds of micro-Amps, as determined by the smart pullup resistor values.
The fall time (t
fA
, t
fB
) of a signal depends on the edge rate and output impedance of the external device driving
the SDIO I/Os, as well as the capacitive loading on these lines.
Similarly, the t
pd
and max data rates also depend on the output impedance of the external driver. The values for
t
fA
, t
fB
, t
pd
, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic I
CC
,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TWL1200 SDIO output sees, so it is recommended that this lumped-load capacitance be
considered and kept below 75 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other
adverse system-level affects.
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