Datasheet

SDA
SCL
Stop Start
Data
t1
t6
t7
t2
t8
t6
t3
t4
t5
Stop
Change
Data
TVP5158, TVP5157, TVP5156
www.ti.com SLES243G –JULY 2009–REVISED APRIL 2013
5.9 I
2
C Host Port Timing
(1)
NO. PARAMETER MIN TYP MAX UNIT
t1 Bus free time between STOP and START 1.3 µs
t2 Data Hold time 0 0.9 µs
t3 Data Setup time 100 ns
t4 Setup time for a (repeated) START condition 0.6 µs
t5 Setup time for a STOP condition 0.6 ns
t6 Hold time (repeated) START condition 0.6 µs
t7 Rise time SDA and SCL signal 250 ns
t8 Fall time SDA and SCL signal 250 ns
C
b
Capacitive load for each bus line 400 pF
f
I2C
I
2
C clock frequency 400 kHz
(1) Specified by design
Figure 5-2. I
2
C Host Port Timing
Copyright © 2009–2013, Texas Instruments Incorporated Electrical Specifications 95
Submit Documentation Feedback
Product Folder Links: TVP5158 TVP5157 TVP5156