Datasheet

t5
Valid Data Valid Data
90%
10%
t3
t4
90%
10%
OCLK_P
DVO_x_[7:0]
t1,t2
TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
5.8 Video Output Clock and Data Timing
10-pF load for 27 MHz and 54 MHz, 6-pF load for 108 MHz
NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Duty cycle, OCLK_P/OCLK_N ≤50%, OCLK_P/OCLK_N = 108 MHz 44 50 55 %
90% to 10%, OCLK_P/OCLK_N = 27 MHz 1.4 ns
t3 Fall time, OCLK_P/OCLK_N
90% to 10%, OCLK_P/OCLK_N = 108 MHz 1.15 ns
10% to 90%, OCLK_P/OCLK_N = 27 MHz 1.4 ns
t4 Rise time, OCLK_P/OCLK_N
10% to 90%, OCLK_P/OCLK_N = 108 MHz 1.15 ns
90% to 10%, Data = 27 MHz 3.4 ns
t1 Fall time, Data
90% to 10%, Data = 108 MHz 2.9
10% to 90%, Data = 27 MHz 4.2 ns
t2 Rise time, Data
10% to 90%, Data = 108 MHz 3.4
50%, OCLK_P/OCLK_N = 27 MHz 1.9 4.86 ns
Propagation delay from falling edge of
t5
OCLK_P/OCLK_N
50%, OCLK_P/OCLK_N = 108 MHz 0.22 1.5 ns
Figure 5-1. Video Output Clock and Data Timing
5.8.1 Video Input Clock and Data Timing
NOTE
Video Cascade Modes: Timing is ensured by design at 27/54MHz input frequency with input trace
delays < 2 ns.
94 Electrical Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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