Datasheet

TVP5158, TVP5157, TVP5156

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SLES243G –JULY 2009–REVISED APRIL 2013

Table 4-95. Decoder Read Enable

Subaddress FFh

Default 01h

7 6 5 4 3 2 1 0

Decoder Auto

Reserved Addr Auto Incr Decoder 4 Decoder 3 Decoder 2 Decoder 1

Incr

This register controls which of the four decoder cores responds to I

C read transactions. A 1 in the corresponding bit position enables the

decoder to respond to read commands. A 1 in Decoder Auto Increment reads the next byte from the next enabled decoder. If Decoder Auto

Increment is 0 and more than one decoder is enabled for reading, then only the lowest numbered decoder responds. A 1 in Address Auto

Increment causes the subaddress to increment after read(s) of the current subaddress are completed.

The following table shows how the address auto-increment and decoder auto-increment functions operate when a multi-byte I

C read

transaction occurs. For this example, decoders 2, 3 and 4 are enabled for reads, the subaddress is 0xA0, and 8 bytes of data are read.

Decoder Auto Incr 0 0 1 1

Addr Auto Incr 0 1 0 1

Data Dec Addr Dec Addr Dec Addr Dec Addr

1st 2 A0 2 A0 2 A0 2 A0

2nd 2 A0 2 A1 3 A0 3 A0

3rd 2 A0 2 A2 4 A0 4 A0

4th 2 A0 2 A3 2 A0 2 A1

5th 2 A0 2 A4 3 A0 3 A1

6th 2 A0 2 A5 4 A0 4 A1

7th 2 A0 2 A6 2 A0 2 A2

8th 2 A0 2 A7 3 A0 3 A2

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