Datasheet

TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
Table 4-91. Interrupt Status
Subaddress F2h
Default Read Only
7 6 5 4 3 2 1 0
Reserved Sig_Present Weak_Sig V_Lock Macrovision Vid_Std Reserved
The host interrupt status register represents the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical
AND between the raw status and mask bits. The external interrupt pin is derived from this register as an OR function of all non-masked
interrupts in this register.
Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding
bits in the interrupt clear register.
Sig_Present
Signal present change interrupt. This interrupt is asserted whenever there is a change in the signal present status (bit 7 of register
01h).
0 Not available
1 Available
Weak_Sig
Weak signal change interrupt. This interrupt is asserted whenever there is a change in the weak signal status (bit 6 of register 01h).
0 Not available
1 Available
V_Lock
Vertical lock change interrupt. This interrupt is asserted whenever there is a change in the vertical lock status (bit 2 of register 00h).
0 Not available
1 Available
Macrovision
Macrovision change interrupt. This interrupt is asserted whenever there is a change in the Macrovision detection status (bits 2:0 of
register 01h).
0 Not available
1 Available
Vid_Std
Video standard change interrupt. This interrupt is asserted whenever there is a change in the detected video standard (bits 2:0 of
register 0Ch).
0 Not available
1 Available
86 Internal Control Registers Copyright © 2009–2013, Texas Instruments Incorporated
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