Datasheet

TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
Table 4-72. OFM Channel Select 2
Subaddress B4h
Default E4h
7 6 5 4 3 2 1 0
2nd_Chan_Sel_Port_B 1st_Chan_Sel_Port_B 2nd_Chan_Sel_Port_A 1st_Chan_Sel_Port_A
This register only needs to be written to video decoder core 0. OFM channel select by video port in 2-Ch mode.
2nd_Chan_Sel_Port_B
Second channel select for port B
00 Ch 1
01 Ch 2
10 Ch 3
11 Ch 4 (default)
1st_Chan_Sel_Port_B
First channel select for port B
00 Ch 1
01 Ch 2
10 Ch 3 (default)
11 Ch 4
2nd_Chan_Sel_Port_A
Second channel select for port A
00 Ch 1
01 Ch 2 (default)
10 Ch 3
11 Ch 4
1st_Chan_Sel_Port_A
First channel select for port A
00 Ch 1 (default)
01 Ch 2
10 Ch 3
11 Ch 4
NOTE: Each video port must be set to a different channel.
Table 4-73. OFM Channel Select 3
Subaddress B5h
Default 00h
7 6 5 4 3 2 1 0
Reserved Hybrid_Chan_Sel [2:0]
This register only needs to be written to video decoder core 0.
Hybrid_Chan_Sel [2:0]
OFM channel select for 1-Ch D1 channel in video cascade mode and hybrid format mode.
000 Ch 1 (default)
001 Ch 2
010 Ch 3
011 Ch 4
100 Cascade input from Port C (for video cascade 1st stage only)
101 Reserved
110 Reserved
111 Reserved
76 Internal Control Registers Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TVP5158 TVP5157 TVP5156