Datasheet

TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
Table 4-68. AVD Output Control 1
Subaddress B0h
Default 00h
7 6 5 4 3 2 1 0
Interleave_mode Channel_Mux_Number Output_ type VCS_ID Video_Res_Sel
This register should be written to all four video decoder cores.
Interleave_mode
Interleave mode for multi-channel formats
00 Non-interleaved (a.k.a. 1-Ch mode) – (default)
01 Pixel-interleaved mode (2-Ch and 4-Ch only)
10 Line-interleaved mode
11 Line-interleaved, hybrid mode (adds 1-Ch D1 to selected 4-Ch Half-D1, 4-Ch CIF or 8-Ch CIF format)
Channel_Mux_Number
Number of time-multiplexed channels
00 1-Ch (reserved)
01 2-Ch
10 4-Ch (or 4-Ch Half-D1 or CIF + 1-Ch D1 for line-interleaved, hybrid mode)
8-Ch cascade (format depends on VCS_ID, line-interleaved mode only)
• Line-interleaved mode
– 1st stage: 8-Ch Half-D1 or 8-Ch CIF (video port A)
11 – 2nd stage: 4-Ch Half-D1 or 4-Ch CIF (video port A)
• Line-interleaved, hybrid mode
– 1st stage: 8-Ch CIF + 1-Ch D1 (video port A)
– 2nd stage: 4-Ch CIF (video port A) and 1-Ch D1 (video port B)
Output_type
Output interface type
0 8-bit ITU-R BT.656 interface (default)
1 16-bit ITU-R BT.601 interface (4-Ch D1 and 4-Ch Half-D1 line-interleaved modes only)
VCS_ID
Video cascade stage ID. Set to 0 for normal operation. For line-interleaved mode only.
0 1st stage (channels 1 to 4) (default)
1 2nd stage (channels 5 to 8)
Video_Res_Sel
Video resolution select. Effects multi-channel OFM only.
00 D1 (default)
01 Reserved
10 Half-D1
11 CIF
72 Internal Control Registers Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TVP5158 TVP5157 TVP5156