Datasheet

TVP5158, TVP5157, TVP5156
www.ti.com SLES243G –JULY 2009–REVISED APRIL 2013
Table 4-67. Embedded Sync Offset Control 2
Subaddress AFh
Default 00h
7 6 5 4 3 2 1 0
Offset [7:0]
Offset [7:0]
This register allows the line relationship between the embedded F and V bit signals to be offset from the 656 standard positions,
and moves F relative to V. This register is only applicable to input video signals with a standard number of lines per frame.
0000 0010 +2 lines (maximum setting for NTSC and PAL)
⋮
0000 0001 +1 line
0000 0000 0 line
1111 1111 -1 line
⋮
1111 0001 -15 lines (minimum setting for NTSC)
⋮
1110 1011 -21 lines (minimum setting for PAL)
Copyright © 2009–2013, Texas Instruments Incorporated Internal Control Registers 71
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