Datasheet

TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
Table 4-51. F-Bit and V-Bit Control
Subaddress 89h
Default 16h
7 6 5 4 3 2 1 0
Rabbit Reserved Fast lock F and V [1:0] Phase Det HPLL
Rabbit
Enable "rabbit ear"
0 Disabled (default)
1 Enabled
Fast lock
Enable fast lock where vertical PLL is reset and a 2 second timer is initialized when vertical lock is lost; during timeout the detected
input VS is output.
0 Disabled
1 Enabled (default)
F and V [1:0]
F and V control bits are only enabled for F-bit control mode 01 and 10 (see register 88h)
F and V Lines Per Frame F Bit V Bit
Standard ITU-R BT.656 ITU-R BT.656
00 Non standard-even Forced to 1 Switch at field boundary
Non standard-odd Toggles Switch at field boundary
Standard ITU-R BT.656 ITU-R BT.656
01 (default)
Non standard Toggles Switch at field boundary
Standard ITU-R BT.656 ITU-R BT.656
10
Non standard Pulsed mode Switch at field boundary
11 Reserved
Phase Det
Enable integral-window phase detector
0 Disabled
1 Enabled (default)
HPLL
Enable horizontal PLL to free run
0 Disabled (default)
1 Enabled
Table 4-52. Output Timing Delay
Subaddress 8Ch
Default 00h
7 6 5 4 3 2 1 0
Output timing delay [7:0]
Output timing delay [7:0]
Adjusts delay for AVID start and stop.
0000 1111 +15 pixel delay
0000 0001 +1 pixel delay
0000 0000 0 pixel delay (default)
1111 1111 -1 pixel delay
1111 0000 -16 pixel delay
66 Internal Control Registers Copyright © 2009–2013, Texas Instruments Incorporated
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