Datasheet

TVP5158, TVP5157, TVP5156
www.ti.com SLES243G –JULY 2009–REVISED APRIL 2013
Table 4-6. RAM Version MSB
Subaddress 05h
Default Read only
7 6 5 4 3 2 1 0
RAM version MSB [7:0]
RAM version MSB [7:0]
This register identifies the MSB of the RAM code revision number.
Table 4-7. RAM Version LSB
Subaddress 06h
Default Read only
7 6 5 4 3 2 1 0
RAM version LSB [7:0]
RAM version LSB [7:0]
This register identifies the LSB of the RAM code revision number.
Example:
Patch Release = v02.01.22
ROM Version = 02h
RAM Version MSB = 01h
RAM Version LSB = 22h
Table 4-8. Chip ID MSB
Subaddress 08h
Default Read only
7 6 5 4 3 2 1 0
Chip ID MSB [7:0]
Chip ID MSB[7:0]
This register identifies the MSB of device ID. Value = 51h
Table 4-9. Chip ID LSB
Subaddress 09h
Default Read only
7 6 5 4 3 2 1 0
Chip ID LSB [7:0]
Chip ID LSB [7:0]
This register identifies the LSB of device ID. This value equals 58h for TVP5158, 57h for TVP5157, and 56h for
TVP5156.
Copyright © 2009–2013, Texas Instruments Incorporated Internal Control Registers 47
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