Datasheet
RESETB
(Terminal 3)
Reset
Normal operation
Invalid I C Cycle
2
Valid
260 µs (min)
20 ms (min)
TVP5158, TVP5157, TVP5156
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SLES243G –JULY 2009–REVISED APRIL 2013
3.12 Reset Mode
Terminal 3 (RESETB) is active low signal to hold the decoder into reset. Table 3-18 shows the
configuration of reset mode. Table 3-19 describes the status of the decoder signals during and
immediately after reset. Figure 3-22 shows the reset timing.
After power-up, the device is in an unknown state until properly reset. An active-low reset, Reset B, of
greater than or equal to 20 ms is required following active and stable supply ramp-up. To avoid potential
I
2
C issues, keep SCL and SDA inactive (high) for at least 260 µs after reset goes high. There are no
power sequencing requirements except that all power supplies should become active and stable within
500 ms of each other.
Table 3-18. Reset Mode
RESETB CONFIGURATION
0 Resets the decoder
1 Normal operation
Table 3-19. Reset Sequence
SIGNAL NAME DURING RESET RESET COMPLETED
DVO_A_[7:0], DVO_B_[7:0], DVO_C_[7:0], DVO_D_[7:0], OCLK_P, OCLK_N,
Input High-impedance
INTREQ, I2CA[2:0], BCLK_R, LRCLK_R, SD_R, SD_M, SD_CO
RESETB, SDA, SCL, LRCLK_CI, BCLK_CI, SD_CI, XTAL_IN Input Input
XTAL_OUT, OSC_OUT Output Output
Figure 3-22. Reset Timing
Copyright © 2009–2013, Texas Instruments Incorporated Functional Description 41
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