Datasheet

VSSA

27-MHz

Crystal

27-MHz CLK

Output to other TVP5158

XTAL_IN pin

27-MHz CLK

Output to other TVP5158

XTAL_IN pin

0 W

TVP5158, TVP5157, TVP5156

SLES243G –JULY 2009–REVISED APRIL 2013

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3.11 Clock Circuits

An analog clock multiplier PLL is used to generate a system clock from an external 27-MHz crystal

(fundamental resonant frequency) or external clock reference input. A crystal can be connected across

terminals 99 (XTAL_IN) and 101 (XTAL_OUT), or a 1.8-V external clock input can be connected to

terminal 99. Four horizontal PLLs generate the line-locked sample clock for each video decoder core from

the system clock. Four color PLLs generate the color subcarrier frequency for each video decoder core

from the corresponding line-locked clock. Four vertical PLLs generate the field/frame sync for each video

decoder core. A frequency synthesizer generates the 32.768-MHz audio oversampling clock for each

analog audio input from the system clock.

Figure 3-21 shows the reference clock configurations. For the example crystal circuit shown, the external

capacitors must have the following relationship:

= C

= 2C

– C

STRAY

Where,

STRAY

is the terminal capacitance with respect to ground

is the crystal load capacitance specified by the crystal manufacturer

Figure 3-21. Clock and Crystal Connectivity

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Product Folder Links: TVP5158 TVP5157 TVP5156