Datasheet
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243G –JULY 2009–REVISED APRIL 2013
I
2
C subaddress FFh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder
read enable bit is set, then I
2
C read transactions are sent to the corresponding decoder core.
If more than one decoder is enabled for reads, then the lowest numbered decoder that is enabled
responds to the read transaction. For multi-byte I
2
C read transactions, there are options to auto-increment
the subaddress or to auto-increment through the selected decoders or both.
3.10.1 I
2
C Write Operation
Data transfers occur utilizing the following formats.
An I
2
C master initiates a write operation to the decoder by generating a start condition (S) followed by the
decoder I
2
C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle.
After receiving an acknowledge from the decoder, the master presents the subaddress of the register, or
the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The
decoder acknowledges each byte after completion of each transfer. The I
2
C master terminates the write
operation by generating a stop condition (P).
Step 1 0
I
2
C Start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C General address (master) 1 0 1 1 1 0 X 0
Step 3 9
I
2
C Acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C Write register address (master) Addr Addr Addr Addr Addr Addr Addr Addr
Step 5 9
I
2
C Acknowledge (slave) A
Step 6
(1)
7 6 5 4 3 2 1 0
I
2
C Write data (master) Data Data Data Data Data Data Data Data
Step 7
(1)
9
I
2
C Acknowledge (slave) A
Step 8 0
I
2
C Stop (master) P
(1) Repeat steps 6 and 7 until all data have been written.
3.10.2 I
2
C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
C
master initiates a write operation to the decoder by generating a start condition (S) followed by the
decoder slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledge from the decoder, the master presents the subaddress of the register or the first of a block of
registers it wants to read. After the cycle is acknowledged, the master has the option of generating a stop
condition or not.
In the data phase, an I
2
C master initiates a read operation to the decoder by generating a start condition
followed by the decoder I
2
C slave address (as shown below for a read operation), in MSB first bit order,
followed by a 1 to indicate a read cycle. After an acknowledge from the decoder, the I
2
C master receives
one or more bytes of data from the decoder. The I
2
C master acknowledges the transfer at the end of each
byte. After the last data byte has been transferred from the decoder, the master generates a not
acknowledge followed by a stop.
Copyright © 2009–2013, Texas Instruments Incorporated Functional Description 37
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