Datasheet

LRCLK_R
BCLK_R
SD_R
(a) I
2
S Format
1/f
s
MSB MSB
LRCLK_R
BCLK_R
SD_R
(b) DSP Format
1/f
s
MSB LSB MSB
LSB
LSB
LSB
LSB
LSB
Data 1 Data 2
Data 1 Data 2
TVP5158, TVP5157, TVP5156
www.ti.com SLES243G –JULY 2009–REVISED APRIL 2013
3.9.3 Serial Audio Interface
The timing for the TVP5158 serial audio interface is shown in Figure 3-18. The TVP5158 audio data
output (SD_R) and frame sync pulse (LRCLK) are aligned with the falling edge of the bit clock (BCLK).
The TVP5158 audio data is delayed one BCLK cycles from the falling edge of the frame sync pulse. In the
DSP mode, the TVP5158 frame sync pulse is high for only one BCLK cycle.
Figure 3-18. Serial Audio Interface Timing Diagram
3.9.4 Analog Audio Input Clamping
An internal clamping circuit provides mid-level clamping of all four analog audio inputs to a dc level of
approximately 0.625 V.
Copyright © 2009–2013, Texas Instruments Incorporated Functional Description 33
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