Datasheet

TVP5158, TVP5157, TVP5156
SLES243G JULY 2009REVISED APRIL 2013
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3.8.3.2 4-Ch Line-Interleaved Mode
In 4-Ch line-interleaved mode, the video output data from all 4 channels is multiplexed together on a line
basis. The output resolution of video data can be D1, Half-D1 or CIF. For D1 and Half-D1 output
resolutions, the video output port can be configured to support 8-bit BT.656 or 16-Bit YCbCr 4:2:2 data
with embedded sync. Port DVO_A is used for 8-bit output. Ports DVO_A and DVO_B are used for 16-Bit
output. The output clock OCLK_P is synchronized with all four output ports.
TVP5158 supports multiplexing 4-Ch CIF and 1-Ch D1 data together and then output through DVO_A at
54 MHz. 1-Ch D1 can be from any one of 4 video channels. In typical surveillance applications, CIF
resolution is used for recording and D1 resolution is used for video preview.
TVP5158 also supports multiplexing 4-Ch Half-D1 and 1-Ch D1 data together and then output through
DVO_A at 108 MHz. The backend chip can use Half-D1 to generate CIF format by dropped one field.
Pleas note that the line-interleaved mode does NOT strictly output one line from each decoder channel
sequentially. The order of multiplexed the video line data is based on the availability of video output data
from each decoder channel. Therefore, it is possible to output two consecutive lines from the same
decoder channel or to skip one decoder channel output.
3.8.3.3 8-Ch Line-Interleaved Mode
Two TVP5158 devices can be cascade connected and work as single 8-Ch video decoder. In cascade
mode, the port DVO_C and DVO_D of master TVP5158 (first stage) can be configured as the video input
interface. The DVO_A and DVO_B of master TVP5158 are configured as the output interface for two
devices. This mode is dedicated for the backend chip with extremely limited input ports.
In the video cascade mode, the open-drain interrupt request (INTREQ) outputs from the first and second
stages can be combined using a wired-OR connection.
Typical applications with cascade mode show in the following diagrams.
Figure 3-12 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview.
Figure 3-13 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview.
Figure 3-14 shows the Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF
Preview.
26 Functional Description Copyright © 2009–2013, Texas Instruments Incorporated
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Product Folder Links: TVP5158 TVP5157 TVP5156